CMOS integrated circuit devices are vulnerable to electrostatic discharge (ESD) induced failure. ESD events or spikes are typically short-duration, high-voltage electrical pulses that are caused, for example, by discharge of a static charge. ESD causes failure of a MOS integrated circuit device by overheating components due to overcurrent, breakdown of thin oxide or other conditions. ESD can damage or destroy integrated circuit devices unless measures are taken to reduce ESD effects on the input pins and output pins of the devices. Various techniques have been used to self-protect output buffers or other input-output nodes against ESD failures. Some of these measures include diode clamps, lateral punch-through devices and guard ring collectors around an input-output bonding pad. These circuits are reasonably effective for protecting input circuits but are less effective for protecting output circuits from high transient voltages.
ESD protection structures are classified into two categories including structures to protect of input buffers and structures to protect output buffers and I/O (input and output) nodes. Protection of input buffers is relatively simple because a CMOS gate does not conduct current. Accordingly, a special protection structure is implemented on the input buffer which restricts the gate voltage of a transistor to a maximum of BV.sub.ox --the oxide breakdown voltage--to hold the charges that enter the oxide as low as possible and much lower than Q.sub.BD --the charge which causes breakdown.
In contradistinction, the second category of output buffers and input-output nodes includes structures that are more difficult to protect. This difficultly results because the output buffer may conduct current during ESD stress, and thus may be damaged. Under ESD stress conditions, the protection structure must be designed and layout constructed so that the protection structure discharges the ESD stress without self-damage while the output buffer conducts only a minimum current.
What is needed is an integrated circuit protection structure and fabrication method which improves ESD protection levels, offers ESD protection for ESD spikes in all directions and polarities and requires no additional process steps.